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我想写一个Verilog代码，它会乘以两个浮点数。试图乘以两个尾数通过移位和加法是我遇到麻烦的地方。问题是，当我尝试更新“shift和add”变量C_m_tmp时，没有任何反应（C_m_tmp = C_m_tmp + tmp;）。我忽略了与我的问题无关的任何代码块。任何人都可以告诉我我错了吗？另外在for循环verilog中不工作
`timescale 1ns/1ps
module float_mult(A_m, B_m, C_m);
input [22:0]A_m, B_m;
output [45:0]C_m;
reg [45:0] C_m_tmp;
reg [22:0] A_m_tmp;
reg [22:0] B_m_tmp;
reg [45:0] tmp;
reg [4:0]i;
initial begin
assign C_m_tmp = 46'b0;
end
//need to remove the leading one from mantissas
[email protected] (A_m) begin
A_m_tmp = A_m >> 1;
A_m_tmp = A_m_tmp^23'b10000000000000000000000;
end
[email protected] (B_m) begin
B_m_tmp = B_m >> 1;
B_m_tmp = B_m_tmp^23'b10000000000000000000000;
end
[email protected](A_m_tmp, B_m_tmp) begin
for (i=0; i |